Author Topic: Mach3 plus xylotex wiring  (Read 19512 times)

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Offline Overloaded

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Re: Mach3 plus xylotex wiring
« Reply #30 on: February 18, 2010, 09:16:04 PM »
Here are a couple more tid-bits from Zylotex.

Check the voltage on the X DIR line. A logic 1 must be at .7 * VCC to be recognized at a 1 . Thus if you measure 5V on VCC then a logic 1 would be .7 * 5 = 3.5V for a logic 1. Some motherbaord parallel ports do not reach this voltage level. Almost all PCI add-in parallel port will. The minimum pulse width for the STEP signal is 1 uS (one microsecond). The DIR line must be stable at least 200 ns (nanosecond before the rising edge of the STEP signals, and remain stable for at least 200 ns after the rising esge of the STEP signal. A logic 0 voltage should be .9V or less. The easiest way to test this is with your voltage meter probing the X DIR line. Have software jog the X axis one direction, note the voltage, and jog the other direction, and again note the voltage.

Russ
 :)