As I noted previously, check that you are using the correct step and dir signal polarity.
PoKeys generates motion in timeslots as it is also done by Mach3. Each timeslot (1 ms long) begins with DIR signal being set, then the step pulses follow in such a way that they are 'right-aligned'. To explain this: if one pulse is to be generated in the timeslot:
a) PoKeys internal pulse generator: 20 us before the timeslot end (980 us after setting the DIR signal), the step pulse will start and will be reset with the next timeslot
b) External pulse generator: step pulse will start in the middle of the timeslot and end with the next timeslot
Similarly, if 2 pulses are to be generated:
a) first pulse will be generated approx. in the middle of the timeslot and one at the end of the timeslot
b) first pulse will be generated at 25-50% and the second at 75-100% of the timeslot
And so on... As you can see, there is plenty of time (4us at the maximum speed) between DIR change and STEP pulse start - unless the STEP pulse polarity is inverted. In this case, the driver will interpret the pulse inverted and what should be the end of the pulse will be interpreted as the start of it. Since STEP and DIR outputs are refreshed at the same time in case of external pulse generators, there is no delay between STEP pulse being reset and DIR signal being set or cleared.